Reduce $1,000,000 Chip Respins and
$12,500 per Engineering-Month Delays with a
Hardware Design Audit

Are your IP designs optimized to eliminate and mitigate functional errors, the leading cause* of chip respins? Do you want to reduce months off the time it takes to integrate firmware (embedded software) with your hardware? What risks are hidden in your design? Submit your documentation to be audited against over 200 criteria to uncover hidden risks and determine its audit score. (See a sample report.)

Sample of actual audit findings:

• Interrupt missing to notify firmware that the XXXX count capture had occurred and that firmware should now read it.
• Interrupt bits are mixed in with read/write bits in the XXXX_CTRL Register which could cause firmware defects. Put interrupt bits in a separate register.
• Please document what happens when the counter reaches 0xFFFF FFFF. Will it stop? Will it roll to 0x0000 0000 and stop? Or will it roll and continue counting?

Choose from one of two Hardware Design Audits:

Submit for a bid for a Full Hardware Design Audit by sending the following information to .

1. Name (or code name) of block or IP.
2. Approximate number of pages in the specification.
3. Approximate number of registers in the block or IP.
4. Comments.

Remember, if this audit saves you just one $12,500 engineering man-month among your hardware or firmware engineers, it will have paid for itself. Click here for a printable flyer.

Confidentiality is very important to us; we keep proprietary information and documentation confidential. Onsite audits are available if documents need to stay on the premises.

* Surveys show high rate of respins due to logical and functional errors:

• 70% of respins due to functional errors. Article.
• Functional logic errors in 43% of first-pass chips. Article.
• Survey shows 46% due to logical/functional errors; other surveys 60%. Article.