| Issue #57 |
|
Vregs by Veripool |
| Issue #56 |
|
SpectaReg by PDTi |
| Issue #55 |
|
IDesignSpec by Agnisys Inc. |
| Issue #54 |
|
CSRCompiler by Semifore |
| Issue #53 |
|
Register Design Tools |
| Issue #52 |
|
Football vs. Football |
| Issue #51 |
|
Is Your Safety Net an Afterthought? |
| Issue #50 |
|
The Language Barrier |
| Issue #49 |
|
Dont Change Bit Assignments |
| Issue #48 |
|
Principle 7: Plan Ahead |
| Issue #47 |
|
Principle 6: Design for Contingencies |
| Issue #46 |
|
Principle 5: Anticipate the Impacts |
| Issue #45 |
|
Principle 4: Design for Compatibility |
| Issue #44 |
|
Principle 3: Balance the Load |
| Issue #43 |
|
Principle 2: Set and Adhere to Standards |
| Issue #42 |
|
Principle 1: Collaborate on the Design |
| Issue #41 |
|
Let's All Be Geniuses |
| Issue #40 |
|
Testing Device Drivers |
| Issue #39 |
|
Register Design Eliminates Read-Modify-Write Issues |
| Issue #38 |
|
Limited CPU Support for Read-Modify-Write Operations |
| Issue #37 |
|
The Dangers of Read-Modify-Write |
| Issue #36 |
|
Hardware and Firmware Ambassadors |
| Issue #35 |
|
The One and Only True Method Really? |
| Issue #34 |
|
More on Product-Specific Details |
| Issue #33 |
|
Product-Specific Details |
| Issue #32 |
|
Programmers Wishlists for Hardware Engineers |
| Issue #31 |
|
Using DMA for the Block Itself |
| Issue #30 |
|
Countdown vs. Countup Counters |
| Issue #29 |
|
Analyzing Countdown Timers |
| Issue #28 |
|
Compatibility of New Blocks with Old Device Drivers |
| Issue #27 |
|
Responses to Level-triggered vs. Edge-triggered Interrupts |
| Issue #26 |
|
Level-triggered vs. Edge-triggered Interrupts |
| Issue #25 |
|
Deactivating Optional I/O Signals |
| Issue #24 |
|
Organizational Barriers |
| Issue #23 |
|
More on Resets |
| Issue #22 |
|
Levels of Reset |
| Issue #21 |
|
Accurate Register Specifications |
| Issue #20 |
|
Sniffing I²C |
| Issue #19 |
|
More on Documenting Registers |
| Issue #18 |
|
Documenting Registers |
| Issue #17 |
|
Intangible Benefits |
| Issue #16 |
|
More Troubleshooting Support in DMA Controllers |
| Issue #15 |
|
Using DMA Controllers to Troubleshoot Problems |
| Issue #14 |
|
Managing Platform-Specific Code |
| Issue #13 |
|
The Impacts of Debugging Facilities and Platform-Specific Code |
| Issue #12 |
|
Identifying Chips and Blocks |
| Issue #11 |
|
More on Buffer Zones |
| Issue #10 |
|
Analyzing Buffer Zones |
| Issue #9 |
|
Abiding by Industry Standards |
| Issue #8 |
|
The (not so) Exciting World of Documentation |
| Issue #7 |
|
Designing a Chip for Unplanned Products |
| Issue #6 |
|
Built-in Debugging Support |
| Issue #5 |
|
Accommodating Product Changes |
| Issue #4 |
|
Basic Interrupt Behavior |
| Issue #3 |
|
Balancing How Firmware Waits on Hardware |
| Issue #2 |
|
Different Bit Types in Different Registers |
| Issue #1 |
|
Early Hardware/Firmware Collaboration |
