Book: Hardware/Firmware Interface Design
Book: Hardware/Firmware Interface Design
Gary has authored a book with practical concepts that can be used while designing ASICs, ASSPs, SoCs, and FPGAs, which will solve many firmware programming issues and help avoid chip respins. It contains over 300 best practices, some of which have been discussed in his newsletters. These best practices help you complete your products and projects sooner and more effectively!
Whether you are primarily a hardware engineer or firmware engineer, this book will help you optimize your project or product’s hardware/firmware interface. Key topics covered include register layout, interrupts, timing and performance, aborts, and errors. Real-world case studies help to solidify the principles and best practices and focus you on cleaner designs, shorter schedules, and better implementations.
This joke illustrates a dynamic discussed in the book. How many firmware engineers does it take to change a light bulb? Excuse me, that’s a hardware problem. How many hardware engineers does it take to change a light bulb? Before I answer that, is it possible to work around that problem in firmware?
Before and After
What a hardware/firmware product may have looked like before, compared to what it could look like after following the principles and best practices in the book.
Table of Contents
Links to articles on the subject of the hardware/firmware interface:
1. Introduction
- What Is the Hardware/Firmware Interface?
- What Is a Best Practice?
- “First Time Right” Also Means …
- Target Audience
- Project Life Cycle
- Case Study
2. Principles
- Seven Principles of Hardware/Firmware Interface Design
3. Collaboration
- First Steps
- Formal Collaboration
- Informal Collaboration
4. Planning
- Industry Standards
- Common Version
- Compatibility
- Defects
- Analysis
- Post Mortem
5. Documentation
- Types
- Document Management
- Reviews
- Content
- Registers
- Bits
- Interrupts
- Time
- Errors
- Information
6. Superblock
- Benefits of a Superblock
- Consolidation
- I/O Signals
- Parameterization
7. Design
- Event Notification
- Performance
- Power-On
- Communication and Control
8. Registers
- Addressing
- Bit Assignment
- Data Types
- Hardware Identification
- Communication and Control
9. Interrupts
- Design
- Pending Register
- Enable Register
- Optional Registers
- Interrupt Module Review
- Triggering on Both Edges
- Using the Interrupt Module
10. Aborts, Etc.
- Definitions
- Halts
- Resets
- Aborts
11. Hooks
- Designing for Hooks
- Peek …
- … and Poke
- Monitor
- More Hooks
12. Conclusion
- Key Points
- Benefits
- Seven Principles of Hardware/Firmware Interface Design
- It Finally Works! Let’s Ship It!
12. Deleted: Firmware – Deleted from the printed book due to space constraints. HwFwChapterDeleted.pdf.
A. Appendix A: Best Practices – The best practices are also available electronically. HwFwBestPractices.xls, .csv, or .txt.
B. Appendix B: Bicycle Controller Specification – Sample document discussed in Chapter 5 available electronically. HwFwBikeBlockTemplate.doc.
C. Deleted: Appendix C: Using This Book in a University – Deleted due to space constraints. HwFwBookUseInUniversity.pdf.
D. Appendix D: Glossary Index
- Page ix, Contents, “Appendix C: Using This Book in a University … Available at elsevierdirect.com/companions/9781856176057 or garystringham.com/hwfwbook”
- Page 4, Section 1.1.1, “that allow the same device driver to work
onwith any brand.” - Page 16, Section 1.6.1, “I had the mono video device driver
running onworking with it in less than a week.” - Page 38, Section 3.2.3, “Getting firmware to run
onwith the developing chip.” - Page 85, Section 5.3.2, “return to them their respective
commentsreviewers so they can quickly remind themselves …” - Page 108, Section 5.7, Explanations about interrupt concepts in this section are discussed in detail in chapter 9.
- Page 130, Section 6.1.3, “Huge amounts of efforts are spent to
eekeke out every fraction.” - Page 208, Section 8.4, “This section will discuss ways of helping firmware identify the hardware
it is running on.” - Page 229, Section 9.1.3, “common in old X86 platforms,
and isnow part of the X86.” - Page 231, Section 9.1.5, “and the CPU that
latchedlatches the source signal assertion.” - Page 249-250, Section 9.5.1, Best practices are that there should be at least two flip-flops for the Clock Synchronization of Signal In. The text, the schematic, and the Verilog code should be updated accordingly.
- Page 273, Section 10.4.3, “Unity mono video block
receivedreceives an abort command.” - Page 283, Section 11.2.3, “A DMA controller is often
useused by blocks.” - Page 299, Section 11.6.1, The last sentence refers to a chapter that was removed because of space constraints. It is available here HwFwChapterDeleted.pdf.