Interrupts
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November 30, 2006
Published by Gary Stringham at November 30, 2006
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A common question engineers often wrestle with is how long hardware will take to do a requested task so firmware can take the next step. Engineers implement different designs (both in hardware and firmware) depending on the length of time, and these designs have varying impacts on hardware and firmware […]
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December 30, 2006
Published by Gary Stringham at December 30, 2006
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On an ASIC, my ISR had to write a 1 in one place and a 0 in another place to acknowledge (ack) the interrupt. The hardware engineer I talked to tried to explain how one was an interrupt bit so that is why it needed a 1, but the other […]
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July 31, 2007
Published by Gary Stringham at July 31, 2007
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In last month’s newsletter I talked about analyzing the size of buffers. Now I will discuss the importance of proper management support for buffers – support in terms of status, interrupts, and errors. For example, when should an interrupt be generated on the receiving buffer? When one byte arrives? When […]
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November 29, 2008
Published by Gary Stringham at November 29, 2008
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Inside each block in a chip is an interrupt module that monitors signals from multiple interrupt sources within the block. These interrupt sources can be from state machines, counters, combinatorial logic, external signals, or other such sources. When an interrupt source asserts, it triggers the interrupt module to latch the […]
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December 31, 2008
Published by Gary Stringham at December 31, 2008
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In the last article, I stated “I see no benefit to level-triggered interrupts. … If you believe otherwise, let me know…” and you did. First, a clarification: Your responses let me know that my use of the term “interrupt module” was the source of some confusion about last month’s article. […]
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